M16C30P_07 Datasheet, PDF (157/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
The transfer clock stops momentarily, because an “H” single is applied to the CTS pin,
when the stop bit is verified.
Tc
The transfer clock resumes running as soon as an “L” single is applied to the CTS pin.
Transfer Clock
TE bit in UiC1
“1”
register
“0”
TI bit in UiC1
“1”
register
“0”
“H”
CTSi
“L”
TXDi
Data is set in the UiTB register
Data is transferred from the UiTB register to
the UARTi transmit register
Start bit
Parity
bit
Stop
bit
Pulse stops because the TE bit is set to “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
TXEPT bit in UiC0 ^{“1”}
register
“0”
IR bit in
“1”
SiTIC register
“0”
i=0 to 2
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 1 (parity enabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
CRS bit = 0 (CTS selected)
· UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Tc
Transfer Clock
TE bit in UiC1 ^{“1”}
register
“0”
TI bit in UiC1
“1”
register
“0”
TXDi
Data is set in the UiTB register
Start bit
Data is transferred from the UiTB register to the UARTi transmit register
Stop
Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
TXEPT bit in
“1”
UiC0 register
“0”
IR bit in
“1”
SiTIC register _{“0”}
i=0 to 2
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 1 (2 stop bits)
· CRD bit in UiC0 register = 1 (CTS/RTS disabled)
· UiIRS bit = 0 (an interrupt request occurs when transmit
buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
Figure 15.18 Transmit Operation
Rev.1.22 Mar 29, 2007 Page 141 of 291
REJ09B0179-0122