M16C30P_07 Datasheet, PDF (105/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
13. DMAC
13.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 13.2 lists the DMA Transfer
Cycles. Table 13.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k
Table 13.2 DMA Transfer Cycles
Transfer Unit Bus Width
Access
Address
8-bit Transfers 16-bit
(DMBIT= 1) (BYTE= L)
8-bit
(BYTE = H)
16-bit Transfers 16-bit
(DMBIT= 0) (BYTE = L)
8-bit
(BYTE = H)
— : This condition does not exist.
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Single-Chip Mode
No. of Read
Cycles
1
1
—
—
1
2
—
—
No. of Write
Cycles
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
No. of Read No. of Write
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
Table 13.3 Coefficient j, k
Internal Area
Internal ROM, RAM
No Wait
With Wait
j
1
2
k
1
2
SFR
1-Wait
2
2
External Area
Separate Bus
No Wait
1-Wait
1
2
2
2
Rev.1.22 Mar 29, 2007 Page 89 of 291
REJ09B0179-0122