M16C30P_07 Datasheet, PDF (95/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using
the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts
down the clock derived by dividing the CPU clock using the prescaler. A watchdog timer interrupt is generated when
an underflow occurs in the watchdog timer.
When the main clock source is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be 16
or 128. If a sub-clock is selected for CPU clock, the divide-by-N value for the prescaler is always 2 no matter how the
WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
With main clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (16 or 128) × Watchdog timer count (32768)
CPU clock
With sub-clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (2) × Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period
is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the
watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting
by writing to the WDTS register.
In stop mode, wait mode, and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the
held value when the modes or state are released.
Figure 12.1 shows the Watchdog Timer Block Diagram. Figure 12.2 shows the WDC and WDTS Register.
CPU
clock
HOLD
Prescaler
1/16
CM07 = 0
WDC7 = 0
1/128
CM07 = 0
WDC7 = 1
CM07 = 1
1/2
Write to WDTS register
Internal RESET signal
(“L” active)
CM07: Bit in CM0 register
WDC7: Bit in WDC register
Figure 12.1 Watchdog Timer Block Diagram
Watchdog timer
Set to
“7FFFh”
Watchdog timer
interrupt request
Rev.1.22 Mar 29, 2007 Page 79 of 291
REJ09B0179-0122