M16C30P_07 Datasheet, PDF (96/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
12. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
WDC
Bit Symbol
—
(b4-b0)
Address
000Fh
Bit Name
High-order Bit of Watchdog Timer
After Reset
00XXXXXXb
Function
RW
RO
Cold Start / Warm Start Discrimination 0 : Cold Start
WDC5 _{Flag(1, 2)}
1 : Warm Start
RW
—
Reserved Bit
Set to “0”
(b6)
RW
Prescaler Select Bit
0 : Divided by 16
WDC7
1 : Divided by 128
RW
NOTES :
1. Writing to the WDC register causes the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less
than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.
2. The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only.
Watchdog Timer Start Register ⁽¹⁾
b7
b0
Symbol
Address
After Reset
WDTS
000Eh
Indeterminate
Function
RW
The w atchdog timer is initialized and starts counting after a w rite instruction to this register.
The w atchdog timer value is alw ays initialized to “7FFFh” regardless of w hatever value is
WO
w ritten.
NOTES :
1. Write to the WDTS register after the w atchdog timer interrupt occurs.
Figure 12.2 WDC and WDTS Register
Rev.1.22 Mar 29, 2007 Page 80 of 291
REJ09B0179-0122