M16C30P_07 Datasheet, PDF (142/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
UARTi Transmit/Receive Control Register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0C1, U1C1
03A5h, 03ADh
00XX0010b
Bit Symbol
Bit Name
Function
RW
Transmit Enable Bit
0 : Transmission disabled
TE
1 : Transmission enabled
RW
Transmit Buffer Empty Flag
0 : Data present in UiTB register
TI
1 : No data present in UiTB register
RO
Receive Enable Bit
0 : Reception disabled
RE
1 : Reception enabled
RW
Receive Complete Flag
0 : No data present in UiRB register
RI
1 : Data present in UiRB register
RO
—
Nothing is assigned. When w rite, set to “0”.
(b5-b4) When read, these contents are indeterminate.
—
Data Logic Select Bit ⁽¹⁾
0 : No reverse
UiLCH
1 : Reverse
RW
Error Signal Output Enable Bit
0 : Output disabled
UiERE
1 : Output enabled
RW
NOTES :
1. The UiLCH bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial
I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I²C mode) or “110b” (UART mode, 9-bit transfer
data).
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U2C1
037Dh
00000010b
Bit Symbol
Bit Name
Function
RW
Transmit Enable bit
0 : Transmission disabled
TE
1 : Transmission enabled
RW
Transmit Buffer Empty Flag
0 : Data present in U2TB register
TI
1 : No data present in U2TB register
RO
Receive Enable Bit
0 : Reception disabled
RE
1 : Reception enabled
RW
Receive Complete Flag
0 : No data present in U2RB register
RI
1 : Data present in U2RB register
RO
UART2 Transmit Interrupt Factor 0 : Transmit buffer empty (TI = 1)
U2IRS _{Select Bit}
1 : Transmit is completed (TXEPT = 1)
RW
UART2 Continuous Receive Mode 0 : Continuous receive mode disabled
U2RRM _{Enable Bit}
1 : Continuous receive mode enabled
RW
Data Logic Select Bit ⁽¹⁾
0 : No reverse
U2LCH
1 : Reverse
RW
Error Signal Output Enable Bit
0 : Output disabled
U2ERE
1 : Output enabled
RW
NOTES :
1. The U2LCH bit is enabled w hen the SMD2 to SMD0 bits in the U2MR register are set to “001b” (clock synchronous
serial I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I²C mode) or “110b” (UART mode, 9-bit transfer
data).
Figure 15.8 U0C1 to U2C1 Registers
Rev.1.22 Mar 29, 2007 Page 126 of 291
REJ09B0179-0122