M16C30P_07 Datasheet, PDF (174/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
Table 15.16 Registers to Be Used and Settings in Special Mode 2
Register
UiTB ⁽³⁾
UiRB ⁽³⁾
UiBRG
UiMR ⁽³⁾
UiC0
UiC1
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS ⁽¹⁾
U2RRM ⁽¹⁾
UiLCH
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to “001b”
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TXDi pin output format ⁽²⁾
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Select the LSB first or MSB first
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt factor
Set this bit to “1” to use continuous receive mode
Set this bit to “1” to use inverted data logic
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
UiERE
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
CKPH
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
NODC
Set to “0”
0, 2, 4 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
Select UART0 and UART1 transmit interrupt factor
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special Mode 2.
i = 0 to 2
Rev.1.22 Mar 29, 2007 Page 158 of 291
REJ09B0179-0122