M16C30P_07 Datasheet, PDF (47/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
6. Processor Mode
Processor Mode Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
PM1
Address
0005h
After Reset
00XXX0X0b
Bit Symbol
Bit Name
Function
RW
CS2 Area Sw itch Bit
0 : 08000h to 26FFFh (Block A disable)
PM10 _{(Data Block Enable Bit) (2)}
1 : 10000h to 26FFFh (Block A enable)
RW
—
Nothing is assigned. When w rite, set to “0”. When read, its content is
(b1) indeterminate.
—
—
Reserved Bit
Set to “0”.
(b2)
RW
—
Nothing is assigned. When w rite, set to “0”. When read, its content is
(b3) indeterminate.
—
—
Nothing is assigned. When w rite, set to “0”. When read, its content is
(b4) indeterminate.
—
—
Nothing is assigned. When w rite, set to “0”. When read, its content is
(b5) indeterminate.
—
—
Reserved Bit
Set to “0”.
(b6)
RW
PM17
Wait Bit⁽³⁾
0 : No w ait state
1 : With w ait state (1 w ait)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. Set the PM10 bit to “0” for Mask ROM version and one time flash version. For flash memory version, the PM10 bit
controls w hether Block A is enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as
internal ROM area.
In addition, for the flash memory version and one time flash version, the PM10 bit is automatically set to “1” w hile the
FMR01 bit in the FMR0 register is set to “1” (CPU rew rite mode or the FMSTP bit enabled).
3. When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or internal
ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0” (w ith
w ait state).
Figure 6.2 PM1 Register (1)
Rev.1.22 Mar 29, 2007 Page 31 of 291
REJ09B0179-0122