M16C30P_07 Datasheet, PDF (184/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
16. A/D Converter
16. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to
P0_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the
corresponding port direction bits are set to “0” (= input mode).
When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow from the
VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for ANi, and AN0_i pins (i = 0 to 7).
Table 16.1 shows the Performance of A/D Converter. Figure 16.1 shows the A/D Converter Block Diagram, and
Figures 16.2 and 16.3 show the A/D converter-related registers.
Table 16.1 Performance of A/D Converter
Item
Method of A/D Conversion
Analog input Voltage ⁽¹⁾
Operating clock φAD ⁽²⁾
Resolution
Integral Nonlinearity Error
Operating Modes
Analog Input Pins
A/D Conversion Start
Condition
Conversion Speed
Performance
Successive approximation (capacitive coupling amplifier)
0V to AVCC (VCC1)
fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
8-bit or 10-bit (selectable)
When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7, AN0_0 to AN0_7, ANEX0 and ANEX1 input : ±5LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7, AN0_0 to AN0_7, ANEX0 and ANEX1 input : ±7LSB
One-shot mode and repeat mode
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
• Software trigger
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• External trigger (retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1”
(A/D conversion starts)
• Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
NOTES:
1. Does not depend on use of sample and hold function.
2. φAD frequency must be 10 MHz or less.
When sample & hold function is disabled, φAD frequency must be 250kHz or more.
When sample & hold function is enabled, φAD frequency must be 1MHz or more.
Rev.1.22 Mar 29, 2007 Page 168 of 291
REJ09B0179-0122