M16C30P_07 Datasheet, PDF (179/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Table 15.18 lists the SIM Mode Specifications. Table 15.19 lists the Registers to Be Used and Settings in SIM
Mode.
Table 15.18 SIM Mode Specifications
Item
Transfer Data Format
Transfer Clock
Specification
• Direct format
• Inverse format
• CKDIR bit in U2MR register = 0 (internal clock) : fi/ (16(n+1))
fi = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of U2BRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
fEXT: Input from CLK2 pin n: Setting value of U2BRG register 00h to FFh
Transmission Start
Condition
Before transmission can start, the following requirements must be met
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in U2TB register)
Reception Start Condition
Interrupt Request
Generation Timing ⁽²⁾
Error Detection
Before reception can start, the following requirements must be met
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
When the serial interface finished sending data from the U2TB transfer register
(U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error ⁽¹⁾
This error occurs if the serial interface started receiving the next data before reading
the U2RB register and received the bit one before the last stop bit of the next data
• Framing error ⁽³⁾
This error occurs when the number of stop bits set is not detected
• Parity error ⁽³⁾
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
NOTES:
1. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register does
not change to “1” (interrupt requested).
2. A transmit interrupt request is generated by setting the U2IRS bit to “1” (transmission complete) and U2ERE bit
to “1” (error signal output) in the U2C1 register after reset. Therefore, when using SIM mode, set the IR bit to “0”
(no interrupt request) after setting these bits.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
Rev.1.22 Mar 29, 2007 Page 163 of 291
REJ09B0179-0122