M16C30P_07 Datasheet, PDF (79/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
11.3 Hardware Interrupts
Hardware interrupts are classified into two types − special interrupts and peripheral function interrupts.
11.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
11.3.1.1 NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the
NMI interrupt, refer to the 11.7 NMI Interrupt.
11.3.1.2 DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
11.3.1.3 Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the
watchdog timer. For details about the watchdog timer, refer to the 12. Watchdog Timer.
11.3.1.4 Single-Step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
11.3.1.5 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated
by the RMAD0 to RMAD1 register that corresponds to one of the AIER0 or AIER1 bit in the AIER register
which is “1” (address match interrupt enabled). For details about the address match interrupt, refer to the 11.9
Address Match Interrupt.
11.3.2 Peripheral Function Interrupts
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is
acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 11.2 Relocatable Vector
Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.
Rev.1.22 Mar 29, 2007 Page 63 of 291
REJ09B0179-0122