M16C30P_07 Datasheet, PDF (143/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
UCON
03B0h
X0000000b
Bit Symbol
Bit Name
Function
UART0 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
U0IRS _{Select Bit}
1 : Transmission completed (TXEPT = 1)
U1IRS
U0RRM
UART1 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
Select Bit
1 : Transmission completed (TXEPT = 1)
UART0 Continuous Receive
Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
UART1 Continuous Receive
U1RRM _{Mode Enable Bit}
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
CLKMD0
UART1 CLK/CLKS Select Bit 0
Effective w hen CLKMD1 = 1
0 : Clock output f rom CLK1
1 : Clock output f rom CLKS1
CLKMD1
RCSP
UART1 CLK/CLKS Select Bit 1 ⁽¹⁾ 0 : CLK output is only CLK1
1 : Transf er clock output f rom multiple pins
Separate UART0
_____ _____
CTS/RTS Bit
function selected
_____ _____
0 : CTS/RTS shared pin
_____ _____
1 : CTS/RTS separated
(CTS0 supplied f rom the P6_4 pin)
—
Nothing is assigned. When w rite, set to “0”.
(b7) When read, its content is indeterminate.
NOTES :
1. When using multiple transfer clock output pins, make sure the follow ing conditions are met:
CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
U0SMR to U2SMR
036Fh, 0373h, 0377h
X0000000b
Bit Symbol
Bit Name
Function
I²C Mode Select Bit
IICM
0 : Other than I²C mode
1 : I²C mode
ABC
Arbitration Lost Detecting Flag 0 : Update per bit
Control Bit
1 : Update per byte
Bus Busy Flag
BBS
—
Reserved Bit
(b3)
0 : STOP condition detected
1 : START condition detected (busy)
Set to “0”
ABSCS
ACSE
Bus Collision Detect Sampling
Clock Select Bit
Auto Clear Function Select Bit
of Transmit Enable Bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj ⁽²⁾
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
Transmit Start Condition Select 0 : Not synchronized to RXDi
SSS _Bit
1 : Synchronized to RXDi ⁽³⁾
—
Nothing is assigned.
(b7) When w rite, set to “0”. When read, its content is indeterminate.
NOTES :
1. The BBS bit is set to “0” by w riting “0” in a program (Writing “1” has no effect).
2. Underflow signal of timer A0 in UART2.
3. When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).
Figure 15.9 UCON and UiSMR Registers
Rev.1.22 Mar 29, 2007 Page 127 of 291
REJ09B0179-0122
RW
RW
RW
RW
RW
RW
RW
RW
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RW
RW
RW
RW⁽¹⁾
RW
RW
RW
RW
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