M16C30P_07 Datasheet, PDF (144/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
UARTi Special Mode Register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR2 to U2SMR2
036Eh, 0372h, 0376h
X0000000b
Bit Symbol
Bit Name
Function
RW
I²C Mode Select Bit 2
IICM2
See Table 15.13 I²C Mode Functions
RW
Clock-Synchronous Bit
0 : Disabled
CSC
1 : Enabled
RW
SCL Wait Output Bit
0 : Disabled
SWC
1 : Enabled
RW
SDA Output Stop Bit
0 : Disabled
ALS
1 : Enabled
RW
UARTi Initialization Bit
0 : Disabled
STAC
1 : Enabled
RW
SCL Wait Output Bit 2
0: Transfer clock
SWC2
1: “L” output
RW
SDA Output Disable Bit
0: Enabled
SDHI
1: Disabled (high-impedance)
RW
—
Nothing is assigned.
(b7) When w rite, set to “0”. When read, its content is indeterminate.
—
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR3 to U2SMR3
036Dh, 0371h, 0375h
000X0X0Xb
Bit Symbol
Bit Name
Function
RW
—
Nothing is assigned.
(b0) When w rite, set “0”. When read, its content is indeterminate.
—
Clock Phase Set Bit
0 : Without clock delay
CKPH
1 : With clock delay
RW
—
Nothing is assigned.
(b2) When w rite, set “0”. When read, its content is indeterminate.
—
Clock Output Select Bit
0 : CLKi is CMOS output
NODC
1 : CLKi is N-channel open drain output
RW
—
Nothing is assigned.
(b4) When w rite, set to “0”. When read, its content is indeterminate.
—
SDAi Digital Delay
DL0
Setup Bit ^{(1, 2)}
DL1
DL2
b7 b6 b5
0 0 0 : Without delay
RW
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
RW
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
RW
NOTES :
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I²C mode. In other than I²C
mode, set these bits to “000b” (no delay).
2. The amount of delay varies w ith the load on SCLi and SDAi pins. Also, w hen using an external clock, the amount of
delay increases by about 100 ns.
Figure 15.10 UiSMR2 and UiSMR3 Registers
Rev.1.22 Mar 29, 2007 Page 128 of 291
REJ09B0179-0122