M16C30P_07 Datasheet, PDF (216/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
19. Flash Memory Version
ROM Code Protect Control Address ⁽⁵⁾
b7 b6 b5 b4 b3 b2 b1 b0
111111
Symbol
ROMCP
Address
0FFFFFh
Factory Setting
FFh ⁽⁴⁾
Bit Symbol
Bit Name
Function
RW
—
Reserved Bit
Set to “1”
(b5-b0)
RW
ROM Code Protect Level 1 Set b7 b6
Bit ^{(1, 2, 3, 4)}
00:
ROMCP1
0 1 : ROM code protection active
RW
10:
1 1 : ROM code protection inactive
NOTES :
1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or
rew riting in parallel I/O mode.
2. Set the bit 5 to bit 0 to “111111b” w hen the ROMCP1 bit is set to a value other than “11b”.
If the bit 5 to bit 0 are set to values other than “111111b”, the ROM code protection may not become active by setting
the ROMCP1 bit to a value other than “11b”.
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode
or CPU rew rite mode.
4. The ROMCP address is set to “FFh” w hen a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is “00h” or “FFh”, the ROM code protect function is disabled.
Figure 19.2 ROMCP Address
Address
0FFFDFh to 0FFFDCh
0FFFE3h to 0FFFE0h
0FFFE7h to 0FFFE4h
0FFFEBh to 0FFFE8h
0FFFEFh to 0FFFECh
0FFFF3h to 0FFFF0h
0FFFF7h to 0FFFF4h
0FFFFBh to 0FFFF8h
0FFFFFh to 0FFFFCh
ID1
Undefined instruction vector
ID2
Overflow vector
BRK instruction vector
ID3
Address match vector
ID4
Single step vector
ID5
Watchdog timer vector
ID6
DBC vector
ID7
NMI vector
ROMCP Reset vector
4 bytes
Figure 19.3 Address for ID Code Stored
Rev.1.22 Mar 29, 2007 Page 200 of 291
REJ09B0179-0122