M16C30P_07 Datasheet, PDF (78/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
11.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
11.2.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
11.2.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation
resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
11.2.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
11.2.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be
specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function
interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT
instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to
“0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning
from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during
instruction execution, and the SP then selected is used.
Rev.1.22 Mar 29, 2007 Page 62 of 291
REJ09B0179-0122