M16C30P_07 Datasheet, PDF (102/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
13. DMAC
DMAi Source Pointer (i = 0, 1) ⁽¹⁾
(b23)
(b19) (b16) (b15)
(b8)
b7
b3
b0 b7
b0 b7
b0
Symbol
SAR0
SAR1
Address
0022h to 0020h
0032h to 0030h
After Reset
Indeterminate
Indeterminate
Function
Setting Range
RW
Set the source address of transfer
00000h to FFFFFh RW
Nothing is assigned. When w rite, set “0”.
When read, their contents are “0”.
—
NOTES :
1. If the DSD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forw ard direction), this register can be w ritten to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this
register. Otherw ise, the value w ritten to it can be read.
DMAi Destination Pointer (i = 0, 1) ⁽¹⁾
(b23)
(b19) (b16) (b15)
(b8)
b7
b3
b0 b7
b0 b7
b0
Symbol
DAR0
DAR1
Address
0026h to 0024h
0036h to 0034h
After Reset
Indeterminate
Indeterminate
Function
Setting Range RW
Set the destination address of transfer
00000h to FFFFFh RW
Nothing is assigned. When w rite, set “0”.
When read, their contents are “0”.
—
NOTES :
1. If the DAD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forw ard direction), this register can be w ritten to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this
register. Otherw ise, the value w ritten to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
(b8)
b7
b0 b7
b0
Symbol
TCR0
TCR1
Function
Address
0029h to 0028h
0039h to 0038h
After Reset
Indeterminate
Indeterminate
Setting Range RW
Set the transfer count minus 1. The w ritten value is stored in the DMAi 0000h to FFFFh
transfer counter reload register, and w hen the DMAE bit in the DMiCON
register is set to “1” (DMA enabled) or the DMAi transfer counter
underflow s w hen the DMASL bit in the DMiCON register is “1” (repeat
RW
transfer), the value of the DMAi transfer counter reload register is
transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
Figure 13.5 SAR0, SAR1, DAR0, DAR1, TCR0 and TCR1 Registers
Rev.1.22 Mar 29, 2007 Page 86 of 291
REJ09B0179-0122