M16C30P_07 Datasheet, PDF (64/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
9. Clock Generating Circuit
System Clock Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol
CM1
Address
0007h
After Reset
00100000b
Bit Symbol
Bit Name
Function
RW
All Clock Stop Control Bit ⁽⁴⁾
0 : Clock on
CM10
1 : All clocks off (stop mode)
RW
—
Reserved Bit
Set to “0”
(b4-b1)
RW
XIN-XOUT Drive Capacity
0 : LOW
CM15 _{Select Bit(2)}
1 : HIGH
RW
Main Clock Division Select Bit 1⁽³⁾
b7 b6
CM16
0 0 : No division mode
RW
0 1 : Division by 2 mode
CM17
1 0 : Division by 4 mode
RW
1 1 : Division by 16 mode
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When entering stop mode from high or middle speed mode, or w hen the CM05 bit is set to “1” (main clock turned off)
in low speed mode, the CM15 bit is set to “1” (drive capability high).
3. Effective w hen the CM06 bit is “0” (CM16 and CM17 bits enable).
4. If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and
XCOUT pins are placed in the high-impedance state.
Figure 9.3 CM1 Register
Peripheral Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol
PCLKR
Address
025Eh
After Reset
00000011b
Bit Symbol
Bit Name
Function
RW
Timers A, B Clock Select Bit (Clock source for the
0 : f2
PCLK0 _{timers A and B)}
1 : f1
RW
SI/O Clock Select Bit
PCLK1 _{(Clock source for UART0 to UART2)}
0 : f2SIO
1 : f1SIO
RW
—
Reserved bit
(b7-b2)
Set to “0”
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
Figure 9.4 PCLKR Register
Rev.1.22 Mar 29, 2007 Page 48 of 291
REJ09B0179-0122