M16C30P_07 Datasheet, PDF (48/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
6. Processor Mode
Processor Mode Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
PM1
Address
0005h
After Reset
00XXX0X0b
Bit Symbol
Bit Name
Function
RW
CS2 Area Sw itch Bit ⁽²⁾
0 : 08000h to 26FFFh
PM10
1 : 10000h to 26FFFh
RW
— Nothing is assigned. When w rite, set to “0”. When read, its content is
(b1) indeterminate.
—
— Reserved Bit
Set to “0”.
(b2)
RW
Internal Reserved Area
(NOTE 5)
PM13 _{Expansion Bit (4)}
RW
— Nothing is assigned. When w rite, set to “0”. When read, its content is
(b4) indeterminate.
—
— Nothing is assigned. When w rite, set to “0”. When read, its content is
(b5) indeterminate.
—
— Reserved Bit
Set to “0”.
(b6)
RW
Wait Bit ⁽³⁾
PM17
0 : No w ait state
1 : With w ait state (1 w ait)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. Set the PM10 bit to “0” for one time flash version.
3. When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or internal
ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0” (w ith
4. The PM13 bit is automatically set to “1” w hen the FMR01 bit in the FMR0 register is “1” (CPU rew rite mode).
5. The access area is changed by the PM13 bit as listed in the table below .
Access Area
PM13=0
PM13=1
RAM Up to Addresses 00400h to 03FFFh (15 Kbytes The entire area is usable
Internal
ROM Up to Addresses D0000h to FFFFFh (192 KbyteThe entire area is usable
External
Address 04000h to 07FFFh are usable
Address 80000h to CFFFFh are usable
Address 04000h to 07FFFh are reserved
Address 80000h to CFFFFh are reserved
(Memory expansion mode)
Figure 6.3
PM1 Register (2) (M30304GDPFP, M30304GDPGP, M30304GEPFP, M30304GEPGP,
M30302GGPFP, M30302GGPGP)
Rev.1.22 Mar 29, 2007 Page 32 of 291
REJ09B0179-0122