M16C30P_07 Datasheet, PDF (152/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15.1.1.5 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its
logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the
UiRB register. Figure 15.15 shows Serial Data Logic Switching.
(1) When The UiLCH Bit in The UiC1 Register = 0 (No Reverse)
“H”
Transfer Clock
“L”
TXDi ^{“H”}
(No Reverse) “L”
D0 D1 D2 D3 D4 D5 D6 D7
(2) When The UiLCH Bit = 1 (Reverse)
“H”
Transfer Clock
“L”
TXDi ^{“H”}
(Reverse) “L”
D0 D1 D2 D3 D4 D5 D6 D7
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UFORM bit = 0
(LSB first).
i = 0 to 2
Figure 15.15 Serial Data Logic Switching
15.1.1.6 Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output pins
(see Figure 15.16). This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
IN
IN
CLK
CLK
Transfer enabled
when the CLKMD0
bit in the UCON
register = 0
Transfer enabled
when the CLKMD0
bit = 1
NOTES :
1. This applies to the case where the CKDIR bit in the U1MR register= 0
(internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
Figure 15.16 Transfer Clock Output from Multiple Pins
Rev.1.22 Mar 29, 2007 Page 136 of 291
REJ09B0179-0122