M16C30P_07 Datasheet, PDF (63/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
9. Clock Generating Circuit
System Clock Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
CM0
0006h
01001000b
Bit Symbol
Bit Name
Function
RW
Clock Output Function ^{b1 b0}
CM00 _{Select Bit}
0 0 : I/O port P5_7
RW
(Valid only in single- ^{0 1 : fC output}
CM01 ^{chip mode)}
1 0 : f8 output
RW
1 1 : f32 output
WAIT Mode Peripheral 0 : Do not stop peripheral function clock in w ait mode
CM02 _{Function Clock Stop Bit 1 : Stop peripheral function clock in w ait mode (8)}
RW
XCIN-XCOUT Drive
0 : LOW
CM03 _{Capacity Select Bit (2) 1 : HIGH}
RW
Port XC Select Bit ⁽²⁾ 0 : I/O port P8_6, P8_7
CM04
1 : XCIN-XCOUT generation function ⁽⁹⁾
RW
Main Clock Stop Bit
0 : On
CM05
(3, 10, 11)
1 : Of f ^{(4, 5)}
RW
Main Clock Division
0 : CM16 and CM17 valid
CM06 _{Select Bit 0 (7, 11)}
1 : Division by 8 mode
RW
System Clock Select Bit 0 : Main clock
CM07
(6, 10)
1 : Sub-clock
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. The CM03 bit is set to “1” (high) w hile the CM04 bit is set to “0,” or w hen entered to stop mode.
3. This bit is provided to stop the main clock w hen the low pow er dissipation mode is selected. This bit cannot be used
for detection as to w hether the main clock stopped or not. To stop the main clock, set bits in the follow ing order.
(a) Set the CM07 bit to “1” (Sub-clock select) w ith the sub-clock stably oscillating.
(b) Set the CM05 bit to “1” (Stop).
4. During external clock input, Set the CM05 bit to “0” (oscillate).
5. When CM05 bit is set to “1”, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains
connected, the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
6. After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), w ait until the sub-clock oscillates stably before
sw itching the CM07 bit from “0” to “1” (sub-clock).
7. When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
8. The fC32 clock does not stop. During low speed or low pow er dissipation mode, do not set this bit to “1” (peripheral
clock turned off w hen in w ait mode).
9. To use a sub-clock, set this bit to “1”. Also make sure ports P8_6 and P8_7 are directed for input, w ith no pull-ups.
10. To use the main clock as the clock source for the CPU clock, set bits in the follow ing order.
(a) Set the CM05 bit to “0” (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set the CM07 bit to “0”.
11. When the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is
fixed to “1” drive capability High).
Figure 9.2 CM0 Register
Rev.1.22 Mar 29, 2007 Page 47 of 291
REJ09B0179-0122