M16C30P_07 Datasheet, PDF (182/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
Microcomputer
TXD2
RXD2
15. Serial Interface
SIM card
Figure 15.34 SIM Interface Connection
15.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”.
The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling
the TXD2 output low with the timing shown in Figure 15.35. If the R2RB register is read while outputting a
parity error signal, the PER bit is cleared to “0” and at the same time the TXD2 output is returned high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer clock
pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt routine.
Transfer “H”
clock “L”
RXD2 ^{“H”}
“L”
TXD2 ^{“H”}
“L”
RI bit in U2C1 ^{“1”}
register “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(NOTE 1)
This timing diagram applies to the case where the direct format is
implemented.
NOTES :
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 15.35 Parity Error Signal Output Timing
Rev.1.22 Mar 29, 2007 Page 166 of 291
REJ09B0179-0122