M16C30P_07 Datasheet, PDF (85/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
11.5.4 Interrupt Sequence
An interrupt sequence − what are performed over a period from the instant an interrupt is accepted to the instant
the interrupt routine is executed − is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If
an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor
temporarily suspends the instruction being executed, and transfers control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 11.5 shows Time Required for
Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
000000h. Then, the IR bit applicable to the interrupt information is set to “0” (interrupt requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register ⁽¹⁾ within the CPU.
(3) The I, D and U flags in the FLG register become as follows:
• The I flag is set to “0” (interrupt disabled)
• The D flag is set to “0” (single-step interrupt disabled)
• The U flag is set to “0” (ISP selected)
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The temporary register ⁽¹⁾ within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt
routine.
NOTES:
1.Temporary register cannot be modified by users.
CPU clock
Address bus
Data bus
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Address
00000h
Interrupt
information
Indeterminate⁽¹⁾
Indeterminate⁽¹⁾
SP-2
SP-4
vec
vec+2
PC
SP-2
SP-4
vec
vec+2
contents contents contents contents
NOTES :
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Figure 11.5 Time Required for Executing Interrupt Sequence
Rev.1.22 Mar 29, 2007 Page 69 of 291
REJ09B0179-0122