M16C30P_07 Datasheet, PDF (149/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
(1) Example of Transmit Timing (when internal clock is selected)
Tc
Transfer clock
“1”
TE bit in
UiC1 register ^{“0”}
TI bit in
“1”
UiC1 register _{“0”}
“H”
CTSi
“L”
CLKi
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
TCLK
Pulse stops because an “H” signal is
applied to CTSi
Pulse stops because the TE bit is set to “0”
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPT bit in “1”
UiC0 register _{“0”}
IR bit in
“1”
SiTIC register “0”
i = 0 to 2
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· CKDIR bit in UiMR register = 0 (internal clock)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data
taken in at the rising edge of the transfer clock)
· UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
(2) Example of Receive Timing (when external clock is selected)
RE bit in
“1”
UiC1 register “0”
TE bit in
UiC1 register
TI bit in
UiC1 register
RTSi
CLKi
RXDi
RI bit in
UiC1 register
“1”
“0”
Dummy data is set in the to UiTB register
“1”
“0”
Data is transferred from the UiTB register to the UARTi transmit register
“H”
“L”
An “L” signal is applied when
1 / fEXT
the UiRB register is read
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
Data is transferred from the UARTi
“1” _{receive register to the UiRB register}
“0”
Read by the UiRB register
IR bit in
“1”
SiRIC register _{“0”}
OER flag in UiRB “1”
register
“0”
Set to “0” by an interrupt request acknowledgement or by program
i=0 to 2
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input to
as follows:
the CLKi pin before receiving data is high:
· CKDIR bit in UiMR register = 1 (external clock)
· TE bit in UiC0 register = 1 (transmit enabled)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
· RE bit in UiC0 register = 1 (receive enabled)
· CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive _{· Write dummy data to the UiTB register}
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 15.12 Transmit and Receive Operation
Rev.1.22 Mar 29, 2007 Page 133 of 291
REJ09B0179-0122