M16C30P_07 Datasheet, PDF (164/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
Table 15.11 Registers to Be Used and Settings in I²C Mode (1)
Register
Bit
UiTB
UiRB ⁽³⁾
UiBRG
UiMR ⁽³⁾
UiC0
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
UiC1
UiSMR
CRS
TXEPT
CRD ⁽⁴⁾
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS ⁽¹⁾
U2RRM ⁽¹⁾,
UiLCH, UiERE
IICM
ABC
UiSMR2
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
Function
Master
Slave
Set transmission data
Set transmission data
Reception data can be read
Reception data can be read
ACK or NACK is set in this bit
ACK or NACK is set in this bit
Arbitration lost detection flag
Invalid
Overrun error flag
Overrun error flag
Set a bit rate
Invalid
Set to “010b”
Set to “010b”
Set to “0”
Set to “1”
Set to “0”
Set to “0”
Select the count source for the UiBRG
register
Invalid
Invalid because CRD = 1
Invalid because CRD = 1
Transmit buffer empty flag
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “1” ⁽²⁾
Set to “1” ⁽²⁾
Set to “0”
Set to “0”
Set to “1”
Set to “1”
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
Transmit buffer empty flag
Transmit buffer empty flag
Set this bit to “1” to enable reception
Set this bit to “1” to enable reception
Reception complete flag
Reception complete flag
Invalid
Invalid
Set to “0”
Set to “0”
Set to “1”
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Bus busy flag
Set to “0”
Set to “0”
See Table 15.13 I²C Mode Functions See Table 15.13 I²C Mode Functions
Set this bit to “1” to enable clock
synchronization
Set to “0”
Set this bit to “1” to have SCLi output fixed Set this bit to “1” to have SCLi output fixed
to “L” at the falling edge of the 9th bit of to “L” at the falling edge of the 9th bit of
clock
clock
Set this bit to “1” to have SDAi output Set to “0”
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output
Set to “0”
Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I²C mode.
4. When using UART1 in I²C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the
U1C0 register to “0” (CTS/RTS enable) and the CRS bit to “0” (CTS input).
i=0 to 2
Rev.1.22 Mar 29, 2007 Page 148 of 291
REJ09B0179-0122