M16C30P_07 Datasheet, PDF (178/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
(1) The ABSCS Bit in the U2SMR Register (Bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
TXD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RXD2
Trigger signal is applied to the TA0IN pin
Timer A0
If ABSCS=1, bus collision is determined when timer
A0 (one-shot timer mode) underflows.
(2) The ACSE Bit in the U2SMR Register (Auto clear of transmit enable bit)
Transfer clock
TXD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RXD2
IR bit in BCNIC
register
TE bit in U2C1
register
If ACSE bit = 1 (automatically
clear when bus collision occurs), the
TE bit is cleared to “0”
(transmission disabled) when the
IR bit in the BCNIC register= 1
(unmatching detected).
(3) The SSS Bit in the U2SMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXD2
Transmission enable condition is met
If SSS bit = 1, the serial interface starts sending data at the rising edge ⁽¹⁾ of RXD2
CLK2
TXD2
(NOTE 2)
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
RXD2
NOTES :
1. The falling edge of RXD2 when IOPOL=0; the rising edge of RXD2 when IOPOL =1.
2. The transmit condition must be met before the falling edge ⁽¹⁾ of RXD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 15.32 Bus Collision Detect Function-Related Bits
Rev.1.22 Mar 29, 2007 Page 162 of 291
REJ09B0179-0122