M16C30P_07 Datasheet, PDF (68/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
9. Clock Generating Circuit
9.4 Power Control
Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode
states, except wait mode and stop mode, are called normal operation mode in this document.
9.4.1 Normal Operation Mode
Normal operation mode is further classified into 4 modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and
the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The
higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the
smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must
be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait time in a
program until it becomes oscillating stably.
9.4.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count
source for timers A and B.
9.4.1.2 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
9.4.1.3 Low-speed Mode
The sub clock provides the CPU clock.
The fC32 clock can be used as the count source for timers A and B.
9.4.1.4 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the
CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit becomes “1” (divided by 8 mode). In the low power
dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be
selected when the main clock is operated next.
Table 9.2 Setting Clock Related Bit and Modes
Modes
High-Speed Mode
Medium-
divided by 2
Speed Mode _{divided by 4}
divided by 8
divided by 16
Low-Speed Mode
Low Power Dissipation Mode
CM1 Register
CM17, CM16
00b
01b
10b
−
11b
−
−
CM07
0
0
0
0
0
1
1
CM0 Register
CM06
CM05
0
0
0
0
0
0
1
0
0
0
−
0
1⁽¹⁾
1⁽¹⁾
CM04
−
−
−
−
−
1
1
− : “0” or ”1”
NOTES:
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low
power dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
Rev.1.22 Mar 29, 2007 Page 52 of 291
REJ09B0179-0122