M16C30P_07 Datasheet, PDF (110/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
14. Timers
14.1 Timer A
Figure 14.3 shows a Timer A Block Diagram. Figures 14.4 to 14.6 show registers related to the Timer A. The
Timer A supports the following four modes. Except in event counter mode, Timers A0 to A2 all have the same
function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 2) to select the desired mode.
• Timer Mode:
The timer counts an internal count source.
• Event Counter Mode:
• One-shot Timer Mode:
The timer counts pulses from an external device or overflows and
underflows of other timers.
The timer outputs a pulse only once before it reaches the minimum
count “0000h”.
• Pulse Width Modulation (PWM) Mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus
Select Count Source
f1 or f2 ⁰⁰
f8 ⁰¹
f32 ¹⁰
fC32 ¹¹
TCK1 to TCK0
• Timer
: TMOD1 to TMOD0=00, MR2=0
• One-Shot Timer
: TMOD1 to TMOD0=10
• Pulse Width Modulation : TMOD1 to TMOD0=11
TMOD1 to TMOD0,
MR2
• Timer(gate function) : TMOD1 to TMOD0=00,
MR2=1
• Event counter : TMOD1 to TMOD0=01
Low-Order Bits of Data Bus
8 low-order
bits
Reload Register
8 high-order
bits
Polarity
Selector
TAiIN
TB2 Overflow ⁽¹⁾
TAj Overflow ⁽¹⁾
TAk Overflow ⁽¹⁾
00
01
10
11
TAiTGH to TAiTGL
TAiS
To external
trigger circuit
00
01
11
Decrement
01
Counter
Increment / decrement
Always decrement except
in event counter mode
TAiUD
0
1
TMOD1 to TMOD0
TAiOUT
Pulse Output
MR2
Toggle Flip Flop
i=0 to 2
j=i-1, however, do not set when i=0
k=i+1, however, do not set when i=2
NOTES:
1. Overflow or underflow
TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 2
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
Figure 14.3 Timer A Block Diagram
Rev.1.22 Mar 29, 2007 Page 94 of 291
REJ09B0179-0122