M16C30P_07 Datasheet, PDF (104/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
13. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
RD signal
CPU use
Source
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
RD signal
CPU use
Source Source + 1
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source Source + 1
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
RD signal
CPU use
Source
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
RD signal
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
NOTES :
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 13.6 Transfer Cycles for Source Read
Rev.1.22 Mar 29, 2007 Page 88 of 291
REJ09B0179-0122