M16C30P_07 Datasheet, PDF (90/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
11.5.10 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 11.10 shows the Interrupts Priority Select Circuit.
Priority level of each interrupt
INT1
Timer B2
Timer B0
Timer A1
UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A2
UART0 bus collision
UART1 reception, ACK1
UART0 reception, ACK0
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
Timer A0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
INT4
IPL
Level 0 (initial value)
I flag
Address match
Watchdog timer
DBC
NMI
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock
generating circuit (Figure 9.1 Clock Generation Circuit)
Interrupt request
accepted
Figure 11.10 Interrupts Priority Select Circuit
Rev.1.22 Mar 29, 2007 Page 74 of 291
REJ09B0179-0122