M16C30P_07 Datasheet, PDF (181/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
(1) Transmit Timing
Tc
Transfer clock
TE bit in U2C1
“1”
register
“0”
TI bit in U2C1
“1”
register
“0”
TXD2
Parity Error signal
returned from
Receiving end
RXD2 pin level ⁽²⁾
TXEPT bit in U2C0 “1”
register
“0”
IR bit in S2TIC
“1”
register
“0”
Data is written to the UARTi register (Note 1)
Start
bit
Parity
bit
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Data is transferred from the UiTB
register to the UARi transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An “L” signal is applied from the
SIM card due to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An interrupt routine ^{An interrupt routine detects “H” or “L”}
detects “H” or “L”
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to “0” by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
(2) Receive Timing
Tc
Transfer clock
RE bit in U2C1 ^{“1”}
register
“0”
Transmit Waveform
from the
Transmitting end
TXD2
RXD2 pin level ⁽¹⁾
Start
bit
Parity
bit
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 provides “L” output
due to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
RI bit in U2C1 “1”
register
“0”
IR bit in S2RIC “1”
register
“0”
Read the U2RB register
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
Set to “0” by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.
2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
TxD2 pin and parity error signal from the receiving end, is generated.
3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxD2 pin, is generated.
Figure 15.33 Transmit and Receive Timing in SIM Mode
Rev.1.22 Mar 29, 2007 Page 165 of 291
REJ09B0179-0122