M16C30P_07 Datasheet, PDF (294/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
22. Usage Precaution
22.8.2 Timer B
22.8.2.1 Timer B (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
A value of a counter, while counting, can be read in TBi register at any time. “FFFFh” is read while reloading.
Setting value is read between setting values in TBi register at count stop and starting a counter.
22.8.2.2 Timer B (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2)
register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this register is
read at the same time the counter is reloaded, the read value is always “FFFFh”. If the TBi register is read after
setting a value in it while not counting but before the counter starts counting, the read value is the one that has
been set in the register.
22.8.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2) register before
setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while the TBiS bit = 1
(count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits and a 0 to the MR2 bit.
The IR bit in the TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use
of the MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a
timer overflow occur at the same time, use another timer to count the number of times Timer B has overflowed.
To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and counting the
next count source after setting the MR3 bit to “1” (overflow).
Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor.
When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload
register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and Timer Bi
interrupt request may be generated between a count start and an effective edge input.
For pulse width measurement, pulse widths are successively measured. Use program to check whether the
measurement result is an “H” level width or an “L” level width.
Rev.1.22 Mar 29, 2007 Page 278 of 291
REJ09B0179-0122