M16C30P_07 Datasheet, PDF (51/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
7. Bus
7.2.3 Chip Select Signal
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These pins can
be chosen to function as I/O ports or as CS by using the CS bit in the CSR register.
Figure 7.1 shows the CSR Register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the
CSi pin.
Figure 7.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte mode.
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
A ddres s
After Reset
CSR
0008h
01h
Bit Symbol _{____}
Bit Name
Function
RW
CS0 Output Enable Bit
0 : Chip select output disabled
CS0
(f unctions as I/O port)
RW
____
CS1
CS1 Output Enable Bit
1 : Chip select output enabled
RW
____
CS2 Output Enable Bit
CS2
RW
____
CS3 Output Enable Bit
CS3
RW
CS0W
CS1W
____
CS0 Wait Bit
____
CS1 Wait Bit
0 : With w ait state (1 w ait)
1 : Without w ait state ^{(1, 2)}
RW
RW
____
CS2 Wait Bit
CS2W
RW
____
CS3 Wait Bit
CS3W
RW
NOTES :
_____
____
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to “0”
(w ith w ait state).
2. If the PM17 bit in the PM1 register is set to “1” (w ith w ait state), set the CSiW bit to “0” (w ith w ait state).
Figure 7.1 CSR Register
Rev.1.22 Mar 29, 2007 Page 35 of 291
REJ09B0179-0122