M16C30P_07 Datasheet, PDF (228/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
19. Flash Memory Version
19.3.5 Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit units,
to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D15 to
D8) are ignored.
Table 19.6 Software Commands
Command
Read Array
Read Status Register
Clear Status Register
Program
Block Erase
Lock Bit Program
Read Lock Bit Status
Mode
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
Data
(D15 to D0)
X
xxFFh
X
xx70h
X
xx50h
WA
xx40h
X
xx20h
BA
xx77h
X
xx71h
Second Bus Cycle
Mode
Address
Data
(D15 to D0)
Read
X
SRD
Write
Write
Write
Write
WA
WD
BA
xxD0h
BA
xxD0h
BA
xxD0h
SRD: Data in the SRD register (D7 to D0)
WA: Address to be written (The address specified in the first bus cycle is the same even
address as the address specified in the second bus cycle.)
WD: 16-bit write data
BA: Highest-order block address (must be an even address)
X: Any even address in the user ROM space
xx: 8 high-order bits of command code (ignored)
19.3.5.1 Read Array Command (FFh)
The read array command reads the flash memory.
By writing command code “xxFFh” in the first bus cycle, read array mode is entered. Content of a specified
address can be read in 16-bit units after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents from
multiple addresses can be read consecutively.
19.3.5.2 Read Status Register Command (70h)
The read status register command reads the status register (refer to 19.3.7 Status Register for detail).
By writing command code “xx70h” in the first bus cycle, the status register can be read in the second bus cycle.
Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
19.3.5.3 Clear Status Register Command (50h)
The clear status register command clears the status register. By writing “xx50h” in the first bus cycle, the
FMR07 to FMR06 bits in the FMR0 register are set to “00b” and the SR5 to SR4 bits in the status register are
set to “00b”.
Rev.1.22 Mar 29, 2007 Page 212 of 291
REJ09B0179-0122