M16C30P_07 Datasheet, PDF (80/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
11.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt
vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt
vector. Figure 11.2 shows the Interrupt Vector.
MSB
LSB
Vector address (L)
Low-order address
Vector address (H)
Middle-order address
0000
High-order
address
0000
0000
Figure 11.2 Interrupt Vector
11.4.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 11.1 lists the Fixed
Vector Tables. In the one time flash memory and the flash memory version of microcomputer, the vector
addresses (H) of fixed vectors are used by the ID code check function. For details, refer to the 19.2 Functions
To Prevent Flash Memory from Rewriting .
Table 11.1 Fixed Vector Tables
Interrupt Source
Undefined Instruction (UND instruction)
Overflow (INTO instruction)
BRK Instruction ⁽²⁾
Vector Table Addresses
Address (L) to Address (H)
FFFDCh to FFFDFh
FFFE0h to FFFE3h
FFFE4h to FFFE7h
Reference
M16C/60, M16C/20 Series
software manual
Address Match
Single Step ⁽¹⁾
Watchdog Timer
DBC ⁽¹⁾
NMI
Reset
FFFE8h to FFFEBh
FFFECh to FFFEFh
FFFF0h to FFFF3h
FFFF4h to FFFF7h
FFFF8h to FFFFBh
FFFFCh to FFFFFh
11.9 Address Match Interrupt
12. Watchdog Timer
11.7 NMI interrupt
5. Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
Rev.1.22 Mar 29, 2007 Page 64 of 291
REJ09B0179-0122