M16C30P_07 Datasheet, PDF (103/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
13. DMAC
13.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus
cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
During memory extension and microprocessor modes, it is also affected by the BYTE pin level. Furthermore, the
bus cycle itself is extended by a software wait or RDY signal.
13.1.1 Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address,
the source read cycle consists of one more bus cycle than when the source address of transfer begins with an
even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an
odd address, the destination write cycle consists of one more bus cycle than when the destination address of
transfer begins with an even address.
13.1.2 Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit data bus
(input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice. Therefore,
this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC
is to access the internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC
does it through the data bus width selected by the BYTE pin.
13.1.3 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles
required for that access increases by an amount equal to software wait states.
13.1.4 Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area are affected
by the RDY signal. Refer to 7.2.6 RDY Signal.
Figure 13.6 shows the example of the Transfer Cycles for Source Read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing
accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the
destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) on
Figure 13.6), two source read bus cycles and two destination write bus cycles are required.
Rev.1.22 Mar 29, 2007 Page 87 of 291
REJ09B0179-0122