M16C30P_07 Datasheet, PDF (135/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15. Serial Interface
Serial interface is configured with 3 channels: UART0 to UART2.
15.1 UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figures 15.1 to 15.3 shows the block diagram of UART0 to UART2. Figure 15.4 shows the UARTi Transmit/
Receive Unit.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I²C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART2
• Special mode 4 (SIM mode) : UART2
Figures 15.5 to 15.11 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
Main clock
1/2 ^f2SIO
f1SIO
PCLK1
0
1
f1SIO or f2SIO
1/8
f8SIO
(UART0)
RXD0
RXD polarity
reversing circuit
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 or CLK0 _CKDIR
00
Internal
01
0
10
1
Extenal
U0BRG
register
1 / (n0+1)
1/4
f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
Receive
clock
UART transmission
010, 100, 101, 110
1/16
Clock synchronous type
Transmission
control circuit
001
Clock synchronous type
(when internal clock is selected)
1/2
0
Transmit
clock
Transmit/
receive
unit
CLK0
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is
selected)
CTS/RTS disabled
CTS/RTS selected
CTS0 /
1
RTS0
CRS 0
RCSP
0
0
CTS0 from UART1
1
1
1
Clock synchronous type
(when external clock ^CKDIR
is selected)
RTS0
CTS/RTS disabled
CTS0
VSS CRD
n0: Values set to the U0BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register
RCSP: Bits in UCON register
Figure 15.1 UART0 Block Diagram
TXD
polarity
reversing
circuit
TXD0
Rev.1.22 Mar 29, 2007 Page 119 of 291
REJ09B0179-0122