M16C30P_07 Datasheet, PDF (57/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
7. Bus
7.2.9 External Bus Status When Internal Area Accessed
Table 7.6 shows the External Bus Status When Internal Area Accessed.
Table 7.6 External Bus Status When Internal Area Accessed
Item
SFR Accessed
Internal ROM, RAM Accessed
A0 to A19
Address output
Maintain status before accessed
address of external area or SFR
D0 to D15
When Read High-impedance
High-impedance
When Write Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output ^{Output “H”}
BHE
BHE output
Maintain status before accessed status
of external area or SFR
CS0 to CS3
Output “H”
Output “H”
ALE
Output “L”
Output “L”
7.2.10 Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the
CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always
accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 7.7 Bit
and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Table 7.7 shows the
Bit and Bus Cycle Related to Software Wait. Figure 7.5 shows the Typical Bus Timings Using Software Wait.
Table 7.7 Bit and Bus Cycle Related to Software Wait
Area
Internal RAM, ROM
External Area
PM1 Register
PM17 Bit ⁽³⁾
0
1
0
−
1
CSR Register
CS3W Bit ⁽¹⁾
CS2W Bit ⁽¹⁾
CS1W Bit ⁽¹⁾
CS0W Bit ⁽¹⁾
−
−
1
0
0
Software Wait
Bus Cycle
No wait
1 wait
No wait
1 wait
1 wait
1 BCLK cycle ⁽²⁾
2 BCLK cycles
1 BCLK cycle
(read)
2 BCLK cycles
(write)
2 BCLK cycle ⁽²⁾
2 BCLK cycle
NOTES:
1. To use the RDY signal, set this bit to “0” (with wait state).
2. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
(with wait state). Therefore, the internal RAM and internal ROM are accessed with no wait states,
and all external areas are accessed with one wait state.
3. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with
wait state).
Rev.1.22 Mar 29, 2007 Page 41 of 291
REJ09B0179-0122