M16C30P_07 Datasheet, PDF (137/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
Main clock
1/2 ^f2SIO
f1SIO
1/8
PCLK1
0
1
f1SIO or f2SIO
f8SIO
(UART2)
RXD2
RXD polarity
reversing circuit
Clock source selection
CLK1 to CLK0 _CKDIR
f1SIO or f2SIO ⁰⁰
f8SIO ⁰¹
f32SIO ¹⁰
Internal
0
1
Extenal
U2BRG
register
1 / (n2+1)
1/4
f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16 _{Clock synchronous}
type
Reception
control circuit
001
Receive
clock
UART transmission
1/16 _{010, 100, 101, 110}
Clock synchronous
type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Transmit
clock
Transmit/
receive
unit
CLK2
CTS2 /
RTS2
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is
selected)
CTS/RTS selected
CTS/RTS disabled
1
1
Clock synchronous type
(when external clock is
selected)
CKDIR
RTS2
CRS 0
0
CTS/RTS disabled
CTS2
1
VSS CRD
n2: Values set to the U2BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 15.3 UART2 Block Diagram
TXD
polarity
reversing
circuit ⁽¹⁾
TXD2
Rev.1.22 Mar 29, 2007 Page 121 of 291
REJ09B0179-0122