M16C30P_07 Datasheet, PDF (212/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
19. Flash Memory Version
19.1 Memory Map
The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the
microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space
as the block A. Figure 19.1 shows a Flash Memory Block Diagram.
The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase.
The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes.
Block A is enabled for use by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area at
addresses 10000h to 26FFFh).
The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O
mode (refer to 19.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware reset occurs
while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin (refer to
19.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an “L” signal
is applied to the CNVSS pin. However, the boot ROM area cannot be read.
00F000h
00FFFFh
Block A : 4 Kbytes (4)
0F0000h
0D0000h
Block 7 : 64 Kbytes
Block 5 : 32 Kbytes
ROM
Capacity
192 Kbytes
ROM
Capacity
128 Kbytes
ROM
Capacity
96 Kbytes
0DFFFFh
0E0000h
0E7FFFh
0E8000h
0EFFFFh
0F0000h
0FFFFFh
Block 6 : 64 Kbytes
0F7FFFh
0F8000h
0F9FFFh
0FA000h
0FBFFFh
0FC000h
Block 0-5
(32+8+8+8+4+4) Kbytes
0FDFFFh
0FE000h
0FEFFFh
0FF000h
0FFFFFh
User ROM area
Block 4 : 8 Kbytes
Block 3 : 8 Kbytes
Block 2 : 8 Kbytes
Block 1 : 4 Kbytes
Block 0 : 4 Kbytes
0FF000h
0FFFFFh
4 Kbytes
Boot ROM area
NOTES:
1. The boot ROM area can only be rewritten in parallel input/output mode.
2. To specify a block, use an even address in that block.
3. Shown here is a block diagram during single-chip mode.
4. Block A can be made usable by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area allocated at addresses 10000h to 26FFFh).
Figure 19.1 Flash Memory Block Diagram
Rev.1.22 Mar 29, 2007 Page 196 of 291
REJ09B0179-0122