M16C30P_07 Datasheet, PDF (148/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 15.3
shows pin functions for the case where the multiple transfer clock output pin select function is deselected.
Table 15.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an “H” (If the N-
channel open-drain output is selected, this pin is in a high-impedance state).
Table 15.3 Pin Functions (when not select multiple transfer clock output pin function)
Pin Name
Function
Method of Selection
TXDi (i = 0 to 2) Serial Data Output (Outputs dummy data when performing reception only)
(P6_3, P6_7,
P7_0)
RXDi
(P6_2, P6_6,
P7_1)
Serial Data Input
PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the
PD7 register = 0
(Can be used as an input port when performing transmission only)
CLKi
(P6_1, P6_5,
P7_2)
Transfer Clock
Output
Transfer Clock
Input
CKDIR bit in the UiMR register = 0
CKDIR bit = 1
PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the
PD7 register = 0
CTSi/RTSi
(P6_0, P6_4,
P7_3)
CTS Input
CRD bit in the UiC0 register = 0
CRS bit in the UiC0 register = 0
PD6_0 and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7
register = 0
RTS Output
CRD bit = 0
CRS bit = 1
I/O Port
CRD bit = 1
Table 15.4 P6_4 Pin Functions
Pin Function
P6_4
CTS1
RTS1
CTS0 ⁽¹⁾
CLKS1
U1C0 Register
CRD
1
CRS
−
0
0
0
1
0
0
−
−
Bit Set Value
UCON Register
RCSP CLKMD1 CLKMD0
0
0
−
0
0
−
0
0
−
1
0
−
−
1 ⁽²⁾
1
PD6 Register
PD6_4
Input: 0, Output: 1
0
−
0
−
− : “0” or “1”
NOTES:
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit
in the U0C0 register to “1” (RTS0 selected).
2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
•High if the CLKPOL bit in the U1C0 register = 0
•Low if the CLKPOL bit = 1
Rev.1.22 Mar 29, 2007 Page 132 of 291
REJ09B0179-0122