M16C30P_07 Datasheet, PDF (213/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
19. Flash Memory Version
19.1.1 Boot Mode
The microcomputer enters boot mode when a hardware reset occurs while an “H” signal is applied to the
CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin. A program in the boot ROM area is
executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.
The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-write
mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten according to the system
implemented.
19.2 Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check
function for standard I/O mode to prevent the flash memory from reading or rewriting.
19.2.1 ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/
output mode. Figure 19.2 shows the ROMCP Address. The ROMCP address is located in the user ROM area.
The ROM code protect function is enabled when the ROMCR bits are set to other than “11b”. In this case, set
the bit 5 to bit 0 to “111111b”.
When exiting ROM code protect, erase the block including the ROMCP address by the CPU rewrite mode or
the standard serial I/O mode.
Rev.1.22 Mar 29, 2007 Page 197 of 291
REJ09B0179-0122