M16C30P_07 Datasheet, PDF (83/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
11. Interrupt
INTi (0 to 4) Interrupt Control Register ⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
A ddres s
After Reset
INT3IC ⁽⁴⁾
0044h
XX00X000b
INT4IC ⁽⁴⁾
0049h
XX00X000b
INT0IC to INT2IC
005Dh to 005Fh
XX00X000b
Bit Symbol
Bit Name
Function
RW
Interrupt Priority Level Select Bit
b2 b1 b0
ILV L0
0 0 0 : Level 0 (interrupt disabled)
RW
0 0 1 : Level 1
0 1 0 : Level 2
ILV L1
0 1 1 : Level 3
1 0 0 : Level 4
RW
1 0 1 : Level 5
ILV L2
1 1 0 : Level 6
1 1 1 : Level 7
RW
Interrupt Request Bit
IR
0: Interrupt not requested
1: Interrupt requested
RW⁽¹⁾
Polarity Select Bit
POL
0 : Selects f alling edge ⁽³⁾
1 : Selects rising edge
RW
—
Reserved Bit
Set to “0”.
(b5)
RW
—
Nothing is assigned. When w rite, set to “0”.
(b7-b6) When read, their contents are indeterminate.
—
NOTES :
1. This bit can only be reset by w riting “0” (Do not w rite “1”).
2. To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, refer to 21.5 Precautions for Interrupt.
3. If the IFSRi bit (i = 0 to 4) in the IFSR register are “1” (both edges), set the POL bit in the INTiIC register to “0”
(falling edge).
4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the ILVL2 to
ILVL0 bits in the INT4IC to INT3IC registers to “000b” (interrupts disabled).
Figure 11.4 Interrupt Control Registers (2)
Rev.1.22 Mar 29, 2007 Page 67 of 291
REJ09B0179-0122