M16C30P_07 Datasheet, PDF (286/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
22. Usage Precaution
22.4 Precautions for Power Control
• When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
• Set the MR0 bit in the TAiMR register (i=0 to 2) to “0” (pulse is not output) to use the timer A to exit stop
mode.
• When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not execute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the DMA
transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT
instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead the
instructions following WAIT, and depending on timing, some of these may execute before the microcomputer
enters wait mode.
Program example when entering wait mode
Program Example:
JMP.B
L1
; Insert JMP.B instruction before WAIT instruction
L1:
FSET
I
;
WAIT
; Enter wait mode
NOP
; More than 4 NOP instructions
NOP
NOP
NOP
• When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which sets
the CM10 bit in the CM1 register to Åg1Åh, and then insert at least 4 NOP instructions. When entering
stop mode, the instruction queue reads ahead the instructions following the instruction which sets the
CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop
mode or before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example:
L2:
FSET
BSET
JMP.B
NOP
NOP
NOP
NOP
I
CM10
L2
; Enter stop mode
; Insert JMP.B instruction
; More than 4 NOP instructions
• Wait the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main clock.
• Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub
clock.
Rev.1.22 Mar 29, 2007 Page 270 of 291
REJ09B0179-0122