M16C30P_07 Datasheet, PDF (290/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
22. Usage Precaution
22.6.6 Rewrite the Interrupt Control Register
(a) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
• Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified occurs,
the IR bit in the register may not be set to “1” (interrupt requested), with the result that the interrupt request
is ignored. If such a situation presents a problem, use the instructions shown below to modify the register.
Usable instructions: AND, OR, BCLR, BSET
• Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested).
Therefore, be sure to use the MOV instruction to clear the IR bit.
(c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set
the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the sample program
fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer.
Example 1:Using the NOP instruction to keep the program waiting until the interrupt control
register is modified
INT_SWITCH1:
FCLR I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00h”.
NOP
;
NOP
FSET I
; Enable interrupts.
The number of NOP instruction is as follows.
When using HOLD function : 4.
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00h”.
MOV.W MEM, R0
; Dummy read.
FSET I
; Enable interrupts.
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00h”.
POPC FLG
; Enable interrupts.
22.6.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
Rev.1.22 Mar 29, 2007 Page 274 of 291
REJ09B0179-0122