M16C30P_07 Datasheet, PDF (160/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15.1.2.4 Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received
data has its logic reversed when read from the UiRB register. Figure 15.21 shows Serial Data Logic Switching.
(1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse)
Transfer Clock ^{“H”}
“L”
TXDi ^{“H”}
(No Reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UiLCH Bit = 1 (Reverse)
“H”
Transfer Clock
“L”
TXDi ^{“H”}
(Reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
NOTES :
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge of the transfer clock),
the UFORM bit in the UiC0 register = 0 (LSB first),
the STPS bit in the UiMR register = 0 (1 stop bit) and
the PRYE bit in the UiMR register = 1 (parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Figure 15.21 Serial Data Logic Switching
15.1.2.5 TXD and RXD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/
output data (including the start, stop and parity bits) are inversed. Figure 15.22 shows the TXD and RXD I/O
Polarity Inverse.
(1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse)
Transfer Clock ^{“H”}
“L”
TXDi ^{“H”}
(No Reverse) ^{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi ^{“H”}
(No Reverse) ^{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the IOPOL Bit = 1 (Reverse)
Transfer Clock ^{“H”}
“L”
TXDi ^{“H”}
(Reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi ^{“H”}
(Reverse) ^{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
NOTES :
1. This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the
PRYE bit in the UiMR register = 1 (parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Figure 15.22 TXD and RXD I/O Polarity Inverse
Rev.1.22 Mar 29, 2007 Page 144 of 291
REJ09B0179-0122