M16C30P_07 Datasheet, PDF (166/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
Table 15.13 I²C Mode Functions
Function
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
Factor of Interrupt Number −
6, 7 and 10 ^{(1, 5, 7)}
Factor of Interrupt Number
15, 17 and 19 ^{(1, 6)}
UARTi transmission
Transmission started or
completed (selected by UiIRS)
Factor of Interrupt Number
16, 18 and 20 ^{(1, 6)}
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for Transferring Data
From the UART Reception
Shift Register to the UiRB
Register
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
UARTi Transmission Output Not delayed
Delay
Functions of P6_3, P6_7 and TXDi output
P7_0 Pins
Functions of P6_2, P6_6 and RXDi input
P7_1 Pins
Functions of P6_1, P6_5 and CLKi input or output selected
P7_2 Pins
Noise Filter Width
15ns
Read RXDi and SCLi Pin
Levels
Possible when the corresponding
port direction bit = 0
Initial Value of TXDi and
SDAi Outputs
CKPOL = 0 (H)
CKPOL = 1 (L)
Initial and End Values of SCLi −
DMA1 Factor ⁽⁶⁾
UARTi reception
Store Received Data
1st to 8th bits of the received data
are stored into bits 7 to 0 in the
UiRB register
Read Received Data
The UiRB register status is read
I²C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Start condition detection or stop condition detection
(See Table 15.14 STSPSEL Bit Functions)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
UARTi transmission UARTi transmission
Rising edge of SCLi Falling edge of SCLi
9th bit
next to the 9th bit
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Rising edge of SCLi 9th bit
Falling edge of SCLi Falling and rising
9th bit
edges of SCLi 9th
bit
Delayed
SDAi input/output
SCLi input/output
− (Cannot be used in I²C mode)
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I²C mode ⁽²⁾
H
L
Acknowledgment detection (ACK)
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB
register
H
L
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB register.
8th bit is stored into bit 8 in the UiRB
register.
1st to 8th bits are
stored into bits 7 to
0 in the UiRB
register ⁽³⁾
Bits 6 to 0 in the
UiRB register ⁽⁴⁾ are
read as bits 7 to 1.
Bit 8 in the UiRB
register is read as
bit 0.
NOTES:
1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to 22.6 Precautions for Interrupt)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 15.27 STSPSEL Bit Functions.
6. See Figure 15.25 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
i = 0 to 2
Rev.1.22 Mar 29, 2007 Page 150 of 291
REJ09B0179-0122