M16C30P_07 Datasheet, PDF (54/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
7. Bus
7.2.6 RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on the
RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus
cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was
acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is
executed. Figure 7.3 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal. To
use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register to “0” (with wait state).
When not using the RDY signal, the RDY pin must be pulled-up.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
tsu (RDY-BCLK) : RDY Input Setup Time
Figure 7.3 Example in which Wait State was Inserted into Read Cycle by RDY Signal
Rev.1.22 Mar 29, 2007 Page 38 of 291
REJ09B0179-0122