M16C30P_07 Datasheet, PDF (162/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15.1.3 Special Mode 1 (I²C mode)
I²C mode is provided for use as a simplified I²C interface compatible mode. Table 15.10 lists the specifications
of the I²C mode. Table 15.11 to 15.12 lists the registers used in the I²C mode and the register values set. Table
15.13 lists the I²C Mode Functions. Figure 15.24 shows the block diagram for I²C mode. Figure 15.25 shows
Transfer to UiRB Register and Interrupt Timing.
As shown in Table 15.13, the microcomputer is placed in I²C mode by setting the SMD2 to SMD0 bits to
“010b” and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output does
not change state until SCLi goes low and remains stably low.
Table 15.10 I²C Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• During master
CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• During slave
CKDIR bit = 1 (external clock) : Input from SCLi pin
Before transmission can start, the following requirements must be met ⁽¹⁾
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Before reception can start, the following requirements must be met ⁽¹⁾
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Overrun error ⁽²⁾
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does
not change to "1" (interrupt requested).
Rev.1.22 Mar 29, 2007 Page 146 of 291
REJ09B0179-0122