M16C30P_07 Datasheet, PDF (302/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
22. Usage Precaution
22.15 One Time Flash Version
22.15.1 Stop mode
When the MCU enters stop mode, execute the instruction which sets the CM10 bit to “1” (stop mode) after
setting the FMR01 bit to “0” and disabling the DMA transfer.
22.15.2 Wait mode
When shifting to wait mode, set the FMR01 bit to “0” before executing the WAIT instruction.
22.15.3 Operation speed
Before the FMR01 bit is set to “1” , set the CM11 bit in the CM1 register to “0” (main clock), select 10 MHz or
less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register. Also,
set the PM17 bit in the PM1 register to “1” (with wait state).
22.15.4 Prohibited Instructions
The following instructions cannot be used when the FMR01 bit is set to “1” because they reference data in the
flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
22.15.5 Interrupts
When the FMR01 bit is set to “1”,
• To use interrupts having vectors in relocatable vector table, the vectors must be relocated in the RAM area.
• The NMI and watchdog timer interrupts are available because the FMR0 and FMR1 registers are forcibly
reset when either interrupt occurs. Allocate jump addresses for individual interrupt routine to fixed vector
table. When the NMI or watchdog timer interrupt occurs, wait until the interrupt routine is completed and
then set the FMR01 bit to “1” in order to set the FMSTP bit in the FMR0 register to “1” again.
• The address match interrupt is not available because the CPU references data in the flash memory.
22.15.6 How to access
Set the FMR01 bit to 1 immediately after setting them first to 0 while a high-level (“H”) signal is applied to the
NMI pin. Do not generate an interrupt or a DMA transfer between setting the FMR01 bit to 0 and setting them
to 1.
Rev.1.22 Mar 29, 2007 Page 286 of 291
REJ09B0179-0122