M16C30P_07 Datasheet, PDF (172/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
15.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 15.15 lists the Special Mode 2 Specifications. Table 15.16 lists the Registers to Be Used and
Settings in Special Mode 2. Figure 15.28 shows Serial Bus Communication Control Example (UART2).
Table 15.15 Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• Master mode
CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Controlled by input/output ports
Before transmission can start, the following requirements must be met ⁽¹⁾
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register)
Before reception can start, the following requirements must be met ⁽¹⁾
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from
the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error ⁽²⁾
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or the
falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive dataClock phase setting
• Selectable from four combinations of transfer clock polarities and phases
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register does
not change to "1" (interrupt requested).
Rev.1.22 Mar 29, 2007 Page 156 of 291
REJ09B0179-0122