UPD78F9234MC-5A4-A Datasheet, PDF (97/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit capture/compare registers (CR000, CR010).
CRC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Generation of reset signal sets the value of CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FF62H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CRC00
0
0
0
0
0
CRC002 CRC001 CRC000
CRC002
0
1
CR010 operating mode selection
Operate as compare register
Operate as capture register
CRC001
0
1
CR000 capture trigger selection
Capture on valid edge of TI010 pin
Capture on valid edge of TI000 pin by reverse phase^Note
CRC000
CR000 operating mode selection
0
Operate as compare register
1
Operate as capture register
Note When the CRC001 bit value is 1, capture is not performed if both the rising and falling edges have been
selected as the valid edges of the TI000 pin.
Cautions 1. The timer operation must be stopped before setting CRC00.
2. When the clear & start mode entered on a match between TM00 and CR000 is selected by
16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a
capture register.
3. To ensure the reliability of the capture operation, the capture trigger requires a pulse
longer than two cycles of the count clock selected by prescaler mode register 00
(PRM00) (refer to Figure 6-17).
User’s Manual U17446EJ5V0UD
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